With constant down-scaling and increasingly demanding requirements to the speed and functionality of ultra-high density integrated circuits, semiconductor devices, such as transistors, diodes, capacitors and the like, need to continuously reduce parasitic resistance between such devices in order to meet performance requirements. A major contributor to parasitic resistance is the contact resistance at the source and drain of the devices in the integrated circuit. To reduce contact resistance, high concentrations of dopants (or dopant species), e.g., phosphorous (P), arsenic (As), boron (B) or the like, are required at the top surface of a device's source and drain (source/drain or S/D) regions.
Additionally, as leading edge integrated circuit technologies scale ever smaller, there is a trend toward higher concentrations of germanium (and other alloying element species) at the surfaces of a devices source/drain regions, partially for strain reasons. This is particularly the case for Ge-containing channels in p-type field effect transistor (p-FET) devices.
Typically, S/D regions of a semiconductor device are epitaxially grown as a series of semiconductor layers to form S/D region epitaxial stacks through a variety of well-known techniques, such as metalorganic chemical vapor deposition or the like. However, S/D regions can be formed by a variety of other well-known techniques, such as implant, plasma, monolayer doping or the like.
Dopant species are generally introduced in-situ during the S/D region formation process. For example, a variety of dopants may be introduced into S/D region epitaxial stacks during the epitaxial growth process. However, it is difficult to dope the S/D regions in-situ in sufficient concentrations to meet state of the art device requirements, particularly in pure germanium (Ge), or silicon-germanium (SiGe) having a high percentage of Ge.
Ion implantation of dopant species, after the initial source/drain formation process, has previously been utilized to further enhance the concentration of dopant in S/D regions. However, high dopant implant doses may cause amorphization and dislocation generation in the S/D regions, which then require subsequent high temperature anneals to reduce the crystalline damage. Such high temperature anneals can undesirably drive the dopant species concentrations away from the surface of the S/D regions as well as modifying the junction gradient in the extension regions. Additionally, ion implantation is not a fully conformal process, which can lead to problematic performance variations from device to device which worsen with reduced pitch and with increased topography.
Additionally, there are various steps in the fabrication of a semiconductor device that frequently require the use of elevated temperature and which occur after the formation of the S/D regions. For example, during gate formation, high temperature annealing steps are often employed. These additional annealing steps will also undesirably diffuse the dopant away from the contact surfaces of the semiconductor's S/D regions and degrade performance.
Accordingly, there is a need for a method to enhance the surface dopant species concentration of source/drain regions in order to decrease contact resistance. There is also a need to enhance the surface concentration of germanium and other alloying element species in source/drain regions. Moreover there is a need for a method to increase such surface dopant species concentrations without damage to the S/D regions and without the need for subsequent high temperature annealing of such S/D regions. More generally, there is a need to minimize the number of annealing steps that S/D regions are subjected to after formation to prevent species outdiffusion.